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Job Opportunity

Job Title: Senior IC Verification Engineer (UVM)
Locations: Tucson, Arizona
Industry: Defense / Aerospace, Semiconductor
Type: Full-time, Perm

Description: Our client company is deploying a Unified Verification Methodology (UVM) based verification capability and is seeking a senior verification engineer to lead all aspects of development, deployment, and execution of the Department’s verification strategy.

Contributions:

    • Participate in the functional verification of ASICs/FPGAs.
    • Lead and mentor teams of verification engineers.
    • Create the verification plan with the Program and RTL designers input and review.
    • Develop the architecture and design of the environment, as well as participating and/or leading a team of engineers to implement the test benches.
    • Create the necessary run and/or post-processing scripts and the overall methodology for the given project (verification environment logistics).
    • Implement the verification environment to include:
      • creation of Constrained Random Agents.
      • creation of Monitors and Scoreboards.
      • incorporation of available models that may exist as C/C++, Verilog or VHDL, etc., and/or creation of those models.
      • creation of functional coverage through use of assertions, etc.
    • Write directed and constrained random tests in parallel with RTL designers to achieve coverage goals.
    • Use of trouble reports and bug tracking.

    Capabilities:

    • A current DoD Secret level security clearance is needed. At a minimum, an Interim Secret clearance will be required in order to start work.
    • BS, MS, or PhD EE degree or other relevant technical discipline.
    • 6-10+ years direct DOD-aerospace industry IC verification experience.
    • Track record of leadership roles, including strong technical & management contributions.
    • Expertise in the creation of plans, schedules, and cost estimates for design verification efforts.
    • Experience in the implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage.
    • UVM testbench implementation knowledge and experience.
    • Experience verifying processor-based systems with the use of application code in a simulation environment.
    • Experience with one or more of the following: UVM, OVM, eRM, VMM.
    • Proficient in C/C++, scripting languages and utilities including Make, Perl, Python, Tcl and Shell scripting.
    • Track record of FPGA/ASIC design and verification using a Linux based development environment.
    • Demonstrated experience and success in applying best in class design methodologies and tools.
    • Demonstrated leadership skills with the ability to lead a design verification team.
    • Experience with SystemC, Questa/Modelsim, VCS and/or NCsim.
    • Knowledge of embedded systems design using Microblaze, Nios, or ARM processors.

    Contact: search@TheNovickGroup.com

    If this opportunity does not meet your needs but you know someone qualified, please refer this opportunity to them. Refer This Opportunity to a Colleague.

 

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